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ADD AND CALL CLI CLO CMP DB DEC DIV END HALT IN INC INT

IRET JMP JNO JNS JNZ JO JS JZ MOD MOV MUL NOP NOT OR ORG

OUT POP POPF PUSH PUSHF RET ROL ROR SHL SHR STI SUB XOR

CPU General Purpose Registers

The CPU is where all the arithmetic and logic (decision making) takes place. The CPU has storage locations called registers. The CPU has flags which indicate zero, negative or overflowed calculations. More information is included in the description of the system architecture.

The CPU registers are called AL, BL, CL and DL.
The machine code names are 00, 01, 02 and 03.

Registers are used for storing binary numbers.

Once the numbers are in the registers, it is possible to perform arithmetic or logic. Sending the correct binary patterns to peripherals like the traffic lights, makes it possible to control them.

; semicolon begins a program comment.

Comments are used to document programs. They are helpful to new programmers joining a team and to existing people returning to a project having forgotten what it is about.

Good comments explain WHY things are being done. Poor comments simply repeat the code or state the totally obvious.

Ram Addresses

Examples [7F] [22] [AL] [CL]

[7F] the contents of RAM at location 7F

[CL] the contents of the RAM location that CL points to. CL contains a number that is used as the address.

The Instruction Set

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ADD - Add two values together

CPU flags are set
Assembler Machine Code Explanation
ADD BL,CL A0 01 02 Add CL to BL. Answer goes into BL
ADD AL,12 B0 00 12 Add 12 to AL. Answer goes into AL

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AND - Logical AND two values together

CPU flags are set
Assembler Machine Code Explanation
AND BL,CL AA 01 02 AND CL with BL. Answer goes into BL
AND AL,12 BA 00 12 AND 12 with AL. Answer goes into AL

The AND rule is that two ones give a one. All other inputs give nought. Look at this example...

       10101010
       00001111
       --------
ANSWER 00001010

The left four bits are masked to 0.

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CALL and RET

CPU flags are NOT set
Assembler Machine Code Explanation
CALL 50 CA 50 Call the procedure at address 50.
The CPU pushes the instruction pointer value IP + 2 onto the stack. Later the CPU returns to this address.
IP is then set to 50.
RET CB The CPU instruction pointer is set to 50. The CPU executes instructions from this address until it reaches the RET command. It then pops the value of IP off the stack and jumps to this address where execution resumes.

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CLI and STI

CPU (I) flag is set/cleared
Assembler Machine Code Explanation
STI FC STI sets the Interrupt flag.
CLI FD CLI clears the Interrupt flag 'I' in the status register. STI sets the interrupt flag 'I' in the status register. The machine code for CLI is FD. The machine code for STI is FC.
If (I) is set, the CPU will respond to interrupts. The simulator generates a hardware interrupt at regular time intervals that you can adjust.
If 'I' is set, there should be an interrupt vector at address [02]. The CPU will jump to the code that this vector points to whenever there is an interrupt.

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CLO

CPU flags are NOT set
Assembler Machine Code Explanation
CLO FE Close unwanted peripheral windows.
CLO is not an x86 command. It closes all unnecessary simulator windows which would otherwise have to be closed manually one by one.

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CMP

CPU flags are set
Assembler Machine Code Explanation
CMP AL,0D DB 00 0D Compare AL with 0D
If the values being compared are ...
EQUAL set the 'Z' flag.
AL less than 0D set the 'S' flag.
AL greater than 0D set no flags.
CMP AL,BL DA 00 01 Compare AL with BL
If the values being compared are ...
EQUAL set the 'Z' flag.
AL less than BL set the 'S' flag.
AL greater than BL set no flags.
CMP CL,[20] DC 02 20 Compare CL with 20
If the values being compared are ...
EQUAL set the 'Z' flag.
CL less than RAM[20] set the 'S' flag.
CL greater than RAM[20] set no flags.

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DB

CPU flags are NOT set
Assembler Machine Code Explanation
DB 22
DB 33
DB 44
DB 0		 22
33
44
00 		Define Byte
DB gives a method for loading values directly into RAM.
DB does not have a machine code.
The numbers or text after DB are loaded into RAM.
Use DB to set up data tables.
DB "Hello"




DB 0		 48
65
6C
6C
6F
00 		ASCII codes are loaded into RAM.




End of text is marked by NULL

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DEC and INC

CPU flags are set
Assembler Machine Code Explanation
INC BL A4 01 Add one to BL.
DEC AL A5 00 Subtract one from AL.

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DIV and MOD

CPU flags are set
Assembler Machine Code Explanation
DIV AL,5 B3 00 05 Divide AL by 5. Answer goes into AL.
DIV differs from the x86 DIV.
DIV AL,BL A3 00 01 Divide AL by BL. Answer goes into AL.
DIV differs from the x86 DIV.
MOD AL,5 B6 00 05 MOD AL by 5.
Remainder after division goes into AL.
MOD is not an x86 command.
MOD AL,BL A6 00 01 MOD AL by BL.
Remainder after division goes into AL.
MOD is not an x86 command.

The x86 DIV calculates div and mod in one command. The answers are put into different registers. This is not possible with the 8 bit simulator so div and mod are separated and simplified.

8 DIV 3 is 3 (with remainder 2). 8 MOD 3 is 2

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END

CPU flags are NOT set
Assembler Machine Code Explanation
END 00 END stops further program execution.
The simulator achieves this by stopping the CPU clock.
END is also an assembler directive.
All code after END is ignored by the assembler.
There should be only one END in a program.

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HALT

CPU flags are NOT set
Assembler Machine Code Explanation
HALT 00 HALT stops further program execution.
The simulator achieves this by stopping the CPU clock.
HALT is not an assembler directive. (See END)
There can be any number of HALT commands in a program.

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IN and OUT

CPU flags are NOT set
Assembler Machine Code Explanation
IN 07 F0 07 Input from port 07. The data is stored in the AL register.
OUT 03 F1 03 Output to port 03. The data comes from the AL register.

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INC and DEC

CPU flags are set
Assembler Machine Code Explanation
INC BL A4 01 Add one to BL.
DEC AL A5 00 Subtract one from AL.

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INT and IRET

CPU flags are NOT set
Assembler Machine Code Explanation
INT 02 CC 02 The return address (IP + 2) is pushed onto the stack.
The stack pointer (SP) is reduced by one.
RAM location 02 contains the address of the Interrupt Handler.
This address is "fetched" and IP is set to it.
IRET CD The return address is popped off the stack.
The stack pointer (SP) is increased by one.
IP is set to the return address popped off the stack.

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JMP

CPU flags are NOT set and the flags are ignored
Assembler Machine Code Explanation
JMP Forward C0 12 Set IP to a new value
Add 12 to IP
The assembler calculates the jump distance.
The biggest possible forward jump is +127.
JMP Back FE Set IP to a new value
Add -2 to IP
FE is -2. This is explained here.
The assembler calculates the jump distance.
The biggest possible backward jump is -128.

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JNO

CPU flags are NOT set. JNO uses the (O) flag.

The (O) flag is set if a calculation gives a result too big to fit in an 8 but register.
Assembler Machine Code Explanation
JNO Forward C6 12 Jump if the (O) flag is NOT set.
If the (O) flag is NOT set, jump forward 12 places.
If the (O) flag is NOT set, add 12 to (IP).
If the (O) flag is set, add 2 to (IP).
The assembler calculates the jump distance.
The biggest possible forward jump is +127.
JNO Back C6 FE Jump if the (O) flag is NOT set.
If the (O) flag is NOT set, jump back 2 places.
If the (O) flag is NOT set, add -2 to (IP).
If the (O) flag is set, add 2 to (IP).
The assembler calculates the jump distance.
The biggest possible backward jump is -128.
FE is -2. This is explained here.

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JNS

CPU flags are NOT set. JNS uses the (S) flag.

The (S) flag is set if a calculation gives a negative result.
Assembler Machine Code Explanation
JNS Forward C4 12 Jump if the (S) flag is NOT set.
If the (S) flag is NOT set, jump forward 12 places.
If the (S) flag is NOT set, add 12 to (IP).
If the (S) flag is set, add 2 to (IP).
The assembler calculates the jump distance.
The biggest possible forward jump is +127.
JNS Back C4 FE Jump if the (S) flag is NOT set.
If the (S) flag is NOT set, jump back 2 places.
If the (S) flag is NOT set, add -2 to (IP).
If the (S) flag is set, add 2 to (IP).
The assembler calculates the jump distance.
The biggest possible backward jump is -128.
FE is -2. This is explained here.

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JNZ

CPU flags are NOT set. JNZ uses the (Z) flag.

The (Z) flag is set if a calculation gives a zero result.
Assembler Machine Code Explanation
JNZ Forward C2 12 Jump if the (Z) flag is NOT set.
If the (Z) flag is NOT set, jump forward 12 places.
If the (Z) flag is NOT set, add 12 to (IP).
If the (Z) flag is set, add 2 to (IP).
The assembler calculates the jump distance.
The biggest possible forward jump is +127.
JNZ Back C2 FE Jump if the (Z) flag is NOT set.
If the (Z) flag is NOT set, jump back 2 places.
If the (Z) flag is NOT set, add -2 to (IP).
If the (Z) flag is set, add 2 to (IP).
The assembler calculates the jump distance.
The biggest possible backward jump is -128.
FE is -2. This is explained here.

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JO

CPU flags are NOT set. JO uses the (O) flag.

The (O) flag is set if a calculation gives a result too big to fit in an 8 but register.
Assembler Machine Code Explanation
JO Forward C5 12 Jump if the (O) flag is set.
If the (O) flag is set, jump forward 12 places.
If the (O) flag is set, add 12 to (IP).
If the (O) flag is NOT set, add 2 to (IP).
The assembler calculates the jump distance.
The biggest possible forward jump is +127.
JO Back C5 FE Jump if the (O) flag is set.
If the (O) flag is set, jump back 2 places.
If the (O) flag is set, add -2 to (IP).
If the (O) flag is NOT set, add 2 to (IP).
The assembler calculates the jump distance.
The biggest possible backward jump is -128.
FE is -2. This is explained here.

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JS

CPU flags are NOT set. JS uses the (S) flag.

The (S) flag is set if a calculation gives a negative result.
Assembler Machine Code Explanation
JS Forward C3 12 Jump if the (S) flag is set.
If the (S) flag is set, jump forward 12 places.
If the (S) flag is set, add 12 to (IP).
If the (S) flag is NOT set, add 2 to (IP).
The assembler calculates the jump distance.
The biggest possible forward jump is +127.
JS Back C3 FE Jump if the (S) flag is set.
If the (S) flag is set, jump back 2 places.
If the (S) flag is set, add -2 to (IP).
If the (S) flag is NOT set, add 2 to (IP).
The assembler calculates the jump distance.
The biggest possible backward jump is -128.
FE is -2. This is explained here.

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JZ

CPU flags are NOT set. JZ uses the (Z) flag.

The (Z) flag is set if a calculation gives a zero result.
Assembler Machine Code Explanation
JZ Forward C1 12 Jump if the (Z) flag is set.
If the (Z) flag is set, jump forward 12 places.
If the (Z) flag is set, add 12 to (IP).
If the (Z) flag is NOT set, add 2 to (IP).
The assembler calculates the jump distance.
The biggest possible forward jump is +127.
JZ Back C1 FE Jump if the (Z) flag is set.
If the (Z) flag is set, jump back 2 places.
If the (Z) flag is set, add -2 to (IP).
If the (Z) flag is NOT set, add 2 to (IP).
The assembler calculates the jump distance.
The biggest possible backward jump is -128.
FE is -2. This is explained here.

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DIV and MOD

CPU Flags are Set
Assembler Machine Code Explanation
DIV AL,5 B3 00 05 Divide AL by 5. Answer goes into AL.
DIV differs from the x86 DIV.
DIV AL,BL A3 00 01 Divide AL by BL. Answer goes into AL.
DIV differs from the x86 DIV.
MOD AL,5 B6 00 05 MOD AL by 5.
Remainder after division goes into AL.
MOD is not an x86 command.
MOD AL,BL A6 00 01 MOD AL by BL.
Remainder after division goes into AL.
MOD is not an x86 command.

The x86 DIV calculates div and mod in one command. The answers are put into different registers. This is not possible with the 8 bit simulator so div and mod are separated and simplified.

8 DIV 3 is 3 (with remainder 2). 8 MOD 3 is 2

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MOV

CPU flags are NOT set
Addressing Mode Assembler Example
Machine Code		 Supported Explanation
Immediate mov al,10

D0 00 10
YES
 Copy 10 into AL
Direct (register) mov al,bl
NO
 Copy BL into AL
Direct (memory) mov al,[50]

D1 00 50
YES
 Copy data from RAM at address 50 into AL. [50] is a pointer to data held in a RAM location.
mov [40],cl

D2 40 02
YES
 Copy data from CL into RAM at address 40. [40] is a pointer to data held in a RAM location.
Indirect mov al,[bl]

D3 00 01
YES
 BL is a pointer to a RAM location. Copy data from that RAM location into AL.
mov [cl],dl

D4 02 03
YES
 CL is a pointer to a RAM location. Copy data from DL into that RAM location.
Indexed mov al,[20 + bl]
NO
 A data table is held in RAM at address 20. BL indexes a data item within the data table. Copy from the data table at address 20+BL into AL.
mov [20 + bl],al
NO
 A data table is held in RAM at address 20. BL indexes a data item within the data table. Copy from AL into the data table at address 20+BL.
Base Register mov al,[bl+si]
NO
 BL points to a data table in memory. SI indexes to a record inside the data table. BL is called the "base register". SI is called the "offset or index". Copy from RAM at address BL+SI into AL.
mov [bl+si],al
NO
 BL points to a data table in memory. SI indexes to a record inside the data table. BL is called the "base register". SI is called the "offset". Copy from AL into RAM at address BL+SI.

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MUL

CPU Flags are Set
Assembler Machine Code Explanation
MUL AL,BL A2 00 01 Multiply AL by BL. The result goes into AL
MUL differs from the x86 MUL.
MUL CL,12 B2 02 12 Multiply CL by 12. The result goes into CL
MUL differs from the x86 MUL.

The x86 MUL places the result into more than one register. This is not possible with the 8 bit simulator so MUL has been simplified. A disadvantage is that an overflow is much more likely to occur.

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NOP

CPU Flags are NOT Set
Assembler Machine Code Explanation
NOP FF Do nothing.
Do nothing for one CPU clock cycle.
This is needed to keep the CPU synchronised with accurately timed electronic circuits.
The CPU might need to delay before the electronics are ready.

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NOT

CPU Flags are Set
Assembler Machine Code Explanation
NOT DL AD 03 Invert all the bits in DL.
If DL contained 01010101, after using NOT it will contain 10101010.

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OR

CPU Flags are Set
Assembler Machine Code Explanation
OR AL,12 BB 00 12 Or 12 with AL. Answer goes into AL
OR BL,CL AB 01 02 Or CL with BL. Answer goes into BL
The OR rule is that two noughts give a nought. All other inputs give one. 
   10101010
OR 00001111
   --------
 = 10101111

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ORG

CPU Flags are NOT Set
Assembler Machine Code Explanation
ORG 50 None ORG is not a CPU instruction. It is an instruction to the assembler to tell it to generate code at a particular address. It is useful for writing procedures and interrupts. It can also be used to specify where in memory, data tables go.

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OUT and IN

CPU Flags are NOT Set
Assembler Machine Code Explanation
IN 07 F0 07 Input from port 07. The data is stored in the AL register.
OUT 03 F1 03 Output to port 03. The data comes from the AL register.

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PUSH, POP, PUSHF and POPF

CPU Flags are NOT Set
Assembler Machine Code Explanation
PUSH AL E0 00 Save AL onto the stack.
Deduct one from the Stack Pointer (SP)
POP BL E1 01 Add one to the stack pointer (SP).
Restore BL from the stack
PUSHF EA Push the CPU flags from the status register (SR) onto the stack. Deduct one from the Stack Pointer (SP)
POPF EB Add one to the stack pointer (SP). POP the CPU flags from the stack into the ststus register (SR).

PUSH saves a byte onto the stack. POP gets it back.The stack is an area of memory that obeys the LIFO rule - Last In First Out. When pushing items onto the stack, remember to pop them off again in exact reverse order. The stack can be used to

  1. hold the return address of a procedure call
  2. hold the return address of an interrupt call
  3. pass parameters into procedures
  4. get results back from procedures
  5. save and restore registers and flags
  6. reverse the order of data.

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RET and CALL

CPU Flags are NOT Set
Assembler Machine Code Explanation
CALL 50 CA 50 Call the procedure at address 50.
The CPU pushes the instruction pointer value IP + 2 onto the stack. Later the CPU returns to this address.
IP is then set to 50.
RET CB The CPU instruction pointer is set to 50. The CPU executes instructions from this address until it reaches the RET command. It then pops the value of IP off the stack and jumps to this address where execution resumes.

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ROL and ROR

CPU Flags are Set
Assembler Machine Code Explanation
ROL AL 9A 00 Rotate the bits in AL left one place.
The leftmost bit is moved to the right end of the byte.
Before ROL 10000110 - After ROL 00001101
ROR DL 9B 03 Rotate the bits in DL right one place.
The rightmost bit is moved to the left end of the byte.
Before ROR 10000110 - After ROR 01000011

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SHL and SHR

CPU Flags are Set
Assembler Machine Code Explanation
SHL AL 9C 00 Shift bits left one place.
The leftmost bit is discarded.
Before SHL 10000110 - After SHL 00001100
SHR DL 9D 03 Shift bits right one place.
The rightmost bit is discarded.
Before SHR 10000110 - After SHR 01000011

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STI and CLI

CPU Flags are NOT Set
Assembler Machine Code Explanation
STI FC STI sets the Interrupt flag.
CLI FD CLI clears the Interrupt flag 'I' in the status register. STI sets the interrupt flag 'I' in the status register. The machine code for CLI is FD. The machine code for STI is FC.
If (I) is set, the CPU will respond to interrupts. The simulator generates a hardware interrupt at regular time intervals that you can adjust.
If 'I' is set, there should be an interrupt vector at address [02]. The CPU will jump to the code that this vector points to whenever there is an interrupt.

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SUB

CPU Flags are Set
Assembler Machine Code Explanation
SUB AL,12 B1 00 12 Subtract 12 from AL. The answer goes into AL.
SUB BL,CL A1 01 02 Subtract CL from BL. The answer goes into BL.

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XOR

CPU Flags are Set
Assembler Machine Code Explanation
XOR AL,12 BC 00 12 12 XOR AL. The answer goes into AL.
XOR BL,CL AC 01 02 CL XOR BL. The answer goes into BL.

XOR can be used to invert selected bits.

     00001111 This is a bit mask.
 XOR 01010101
     --------
     01011010

The left four bits are unaltered. The right four bits are inverted.

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© C Neil Bauers 2003