|
Instruction Set Summary |
AL, BL, CL and DL are eight bit, general purpose registers where data is stored.
Square brackets indicate RAM locations. For example [15] means RAM location 15.
Data can be moved from a register into into RAM and also from RAM into a register.
Registers can be used as pointers to RAM. [BL] is the RAM location that BL points to.
All numbers are in base 16 (Hexadecimal).
Move Instructions. Flags NOT set. |
|||||||||||
| Assembler | Machine Code | Explanation | |||||||||
| MOV | AL,15 | D0 00 15 | AL |
= | 15 |
Copy 15 into AL | |||||
| MOV | BL,[15] | D1 01 15 | BL |
= | [15] |
Copy RAM[15] into BL | |||||
| MOV | [15],CL | D2 15 02 | [15] |
= | CL |
Copy CL into RAM[15] | |||||
| MOV | DL,[AL] | D3 03 00 | DL |
= | [AL] |
Copy RAM[AL] into DL | |||||
| MOV | [CL],AL | D4 02 00 | [CL] |
= | AL |
Copy AL into RAM[CL] | |||||
Direct Arithmetic and Logic. Flags are set. |
|||||||||||
| Assembler | Machine Code | ||||||||||
| ADD | AL,BL | A0 00 01 | AL |
= | AL + BL |
||||||
| SUB | BL,CL | A1 01 02 | BL |
= | BL - CL |
||||||
| MUL | CL,DL | A2 02 03 | CL |
= | CL * DL |
||||||
| DIV | DL,AL | A3 03 00 | DL |
= | DL / AL |
||||||
| INC | DL | A4 03 | DL |
= | DL + 1 |
||||||
| DEC | AL | A5 00 | AL |
= | AL - 1 |
||||||
| AND | AL,BL | AA 00 01 | AL |
= | AL AND BL |
||||||
| OR | CL,BL | AB 03 02 | CL |
= | CL OR BL |
||||||
| XOR | AL,BL | AC 00 01 | AL |
= | AL XOR BL |
||||||
| NOT | BL | AD 01 | BL |
= | NOT BL |
||||||
| ROL | AL | 9A 00 | Rotate bits left. LSB
= MSB |
||||||||
| ROR | BL | 9B 01 | Rotate bits right. MSB = LSB | ||||||||
| SHL | CL | 9C 02 | Shift bits left. Discard
MSB. |
||||||||
| SHR | DL | 9D 03 | Shift bits right. Discaed
LSB. |
||||||||
Immediate Arithmetic and Logic. Flags are set. |
|||||||||||
| Assembler | Machine Code | ||||||||||
| ADD | AL,12 | B0 00 12 | AL |
= | AL + 12 | ||||||
| SUB | BL,15 | B1 01 15 | BL |
= | BL - 15 | ||||||
| MUL | CL,03 | B2 02 03 | CL |
= | CL * 3 | ||||||
| DIV | DL,02 | B6 03 02 | DL |
= | DL / 2 | ||||||
| AND | AL,10 | BA 00 10 | AL |
= | AL AND 10 | ||||||
| OR | CL,F0 | BB 02 F0 | CL |
= | CL OR F0 | ||||||
| XOR | AL,AA | BC 00 AA | AL |
= | AL XOR AA | ||||||
Compare Instructions. Flags are set. |
|||||||||||
| Assembler | Machine Code | Explanation
|
|||||||||
| CMP | AL,BL | DA 00 01 | Set 'Z' flag if AL = BL. Set 'S' flag if AL < BL. |
||||||||
| CMP | BL,13 | DB 01 13 | Set 'Z' flag if BL = 13. Set 'S' flag if BL < 13. |
||||||||
| CMP | CL,[20] | DC 02 20 | Set 'Z' flag if CL = [20]. Set 'S' flag if CL < [20]. |
||||||||
Branch Instructions. Flags NOT set. |
|||||||||||
Depending on the type of
jump, different machine codes can be generated. The CPU flags control these jumps. The 'Z' flag is set if the most recent
|
|||||||||||
| Assembler | Machine Code | Explanation | |||||||||
| JMP | HERE | C0 12 C0 FE |
Increase IP by 12 Decrease IP by 2 (twos complement) |
||||||||
| JZ | THERE | C1 09 C1 9C |
Increase IP by 9 if the 'Z' flag is set. Decrease IP by 100 if the 'Z' flag is set. |
||||||||
| JNZ | A_Place | C2 04 C2 F0 |
Increase IP by 4 if the 'Z' flag is NOT
set. Decrease IP by 16 if the 'Z' flag is NOT set. |
||||||||
| JS | STOP | C3 09 C3 E1 |
Increase IP by 9 if the 'S' flag is set. Decrease IP by 31 if the 'S' flag is set. |
||||||||
| JNS | START | C4 04 C4 E0 |
Increase IP by 4 if the 'S' flag is NOT
set. Decrease IP by 32 if the 'S' flag is NOT set. |
||||||||
| JO | REPEAT | C5 09 C5 DF |
Increase IP by 9 if the 'O' flag is set. Decrease IP by 33 if the 'O' flag is set. |
||||||||
| JNO | AGAIN | C6 04 C6 FB |
Increase IP by 4 if the 'O' flag is NOT
set. Decrease IP by 5 if the 'O' flag is NOT set. |
||||||||
Procedures and Interrupts. Flags NOT set. |
|||||||||||
CALL, RET, INT and IRET are available only in the registered version. |
|||||||||||
| Assembler | Machine Code | Explanation | |||||||||
| CALL | 30 | CA 30 | Save IP on the stack and jump to the procedure at address 30. |
||||||||
| RET | CB | Restore IP from the stack and jump to it. | |||||||||
| INT | 02 | CC 02 | Save IP on the stack and jump to the address (interrupt vector) retrieved from RAM[02]. |
||||||||
| IRET | CD | Restore IP from the stack and jump to it. | |||||||||
Stack Manipulation Instructions. Flags NOT set. |
|||||||||||
| Assembler | Machine Code | Explanation | |||||||||
| PUSH | BL | E0 01 | BL is saved onto the stack. | ||||||||
| POP | CL | E1 02 | CL is restored from the stack. | ||||||||
| PUSHF | EA | SR flags are saved onto the stack. | |||||||||
| POPF | EB | SR flags are restored from the stack. | |||||||||
Input Output Instructions. Flags NOT set. |
|||||||||||
| Assembler | Machine Code | Explanation | |||||||||
| IN | 07 | F0 07 | Data input from I/O port 07 to AL. | ||||||||
| OUT | 01 | F1 01 | Data output to I/O port 07 from AL. | ||||||||
Miscellaneous Instructions. CLI and STI set I flag. |
|||||||||||
| Assembler | Machine Code | Explanation | |||||||||
| CLO | FE | Close visible peripheral windows. | |||||||||
| HALT | 00 | Halt the processor. | |||||||||
| NOP | FF | Do nothing for one clock cycle. | |||||||||
| STI | FC | Set the interrupt flag in the Status Register. | |||||||||
| CLI | FD | Clear the interrupt flag in the Status Register. | |||||||||
| ORG | 40 | Code origin | Assembler directive: Generate code starting
from address 40. |
||||||||
| DB | "Hello" | Define byte | Assembler directive: Store the ASCII codes of 'Hello' into RAM. |
||||||||
| DB | 84 | Define byte | Assembler directive: Store 84 into RAM. | ||||||||
© C Neil Bauers 2003